Recent trends to increase the operating speed of integrated circuit memory devices (e.g., DRAM devices) have focused on techniques to increase the rates at which data can be read from and written into memory cells within the devices. In such devices, sense amplifiers are typically used during reading operations to sense relatively small differential signals and then amplify them to rail-to-rail signal levels (e.g., Vcc and Vss). As will be understood by those skilled in the art, the amplified signals may then be transferred to pairs of input/output lines and then to an output buffer using column decoding techniques. Because sense amplifiers play a significant role in both reading data from and writing data to a memory device, techniques to improve the speed at which sense amplifiers can perform accurate sense and amplify operations have been pursued.
Referring now to FIG. 1, a conventional technique for reading data from and writing data to a memory cell (MC) will be described. In particular, during a reading operation, a word line WL may be driven to a logic 1 level to turn on an NMOS access transistor within the memory cell MC. Charge stored within a storage capacitor may then be transferred through the NMOS access transistor to a bit line BL. If the pair of complementary bit lines BL and /BL have been equalized at a common potential (e.g.,1/2Vcc), then the transfer of charge to the bit line BL will cause the potential of the bit line BL to increase relative to the potential of the complementary bit line /BL. Once this transfer has occurred, a sense amplifier SA can be used to "sense" and then "amplify" the differential potential established across the complementary bit lines. As illustrated, a conventional sense amplifier SA may comprise a pair of serially-connected NMOS transistors and a pair of serially-connected PMOS transistors. The gate electrodes of these transistors are also cross-coupled in the manner illustrated. An NMOS pull-down transistor and a PMOS pull-up transistor are also typically provided. The NMOS pull-down transistor is responsive to signal .phi.SEN and the PMOS pull-up transistor is responsive to signal .phi.SEP. Thus, when signal .phi.SEN is driven to a logic 1 level and signal .phi.SEP is driven to a logic 0 level, node A of the sense amplifier will be driven to Vss and node B of the sense amplifier will be driven to Vcc.
These operations activate the sense amplifier and enable the amplify operation to be performed on the differential signal established across the complementary bit lines BL and /BL. Accordingly, the bit line BL will be driven to Vcc and the complementary bit line /BL will be driven to Vss. The column select signal line CSL can then be driven to a logic 1 level to enable the transfer of the "read" data to the pair of complementary input/output lines IO and /IO. This transfer occurs through the NMOS pass transistors 11 and 12 which are responsive to the column select signal CSL. Alternatively, during a writing operation, a rail-to-rail differential signal established across the complementary input/output lines IO and /IO can be transferred to the complementary bit lines BL and /BL and then sensed and amplified by the sense amplifier SA before being stored within the memory cell MC upon activation of the word line.
Unfortunately, if a data read operation is performed and then followed by a data write operation to the same pair of bit lines and the read data is the opposite of the write data, a significant amount of delay may be incurred in switching (i.e., reversing) the differential signal established across the complementary bit lines BL and /BL and latched by the sense amplifier SA. Thus, notwithstanding the above-described sense amplifier, there continues to be a need for improved memory devices that can switch the value of a differential signal established across a pair of complementary bit lines in a more efficient manner to improve read and write cycle times.